Sarita Adve

From Left to Right - Byn Choi, Siva Kumar Sastry Hari, Sarita Adve, Pradeep Ramachandran,
Man-Lap (Alex) Li, Rakesh Komuravelli, Hyojin Sung

Directed by: Sarita V. Adve

Department of Computer Science
University of Illinois at Urbana-Champaign

Our group's research focus is in computer architecture. We take a full system view of the problems we solve, and so our projects are usually collaborative with faculty and students from many areas, including applications, software, and hardware.

The field of computer architecture is currently undergoing several disruptive changes. Moore's law continues to bestow a wealth of transistors, but converting them into usable performance requires addressing several challenges. Industry has bet that the path to future performance benefits is through parallel (or manycore) computing. However, parallel programming remains a black art that few have been able to master. Further, it is unclear how to build manycore systems that will scale to the levels required, within the needed power budget and with the needed reliability. We are currently working on the following projects to address these challenges in a holistic fashion:

     DPL: Deterministic-by-default Parallel Languages (led by Vikram Adve)
     DeNovo: Rethinking Hardware for Disciplined Parallelism
     SWAT: Designing Resilient Hardware by Treating Software Anomalies

Recent projects:
     RAMP: Reliability-Aware MicroProcessors for hard and soft errors
     ALP: Energy-efficient support for All Levels of Parallelism for emerging multimedia workloads
     GRACE: Global Resource Adaptation through CoopEration for energy in mobile multimedia systems
     Energy and Thermal Management in Data Centers

Some of our most significant previous research contributions are in the following areas:

Memory consistency models: co-developed the memory models for the C++ and Java programming languages, based on our early work on data-race-free models
Hardware reliability: co-developed the concept of lifetime reliability aware architectures and dynamic reliability management
Power management: co-designed GRACE, one of the first systems to implement cross-layer energy management
Memory level parallelism: Some of the first papers on exploiting instruction-level parallelism (ILP) for memory system performance
Evaluation techniques for shared-memory systems with ILP processors: developed the widely used RSIM architecture simulator


Home People Research Current DeNovo SWAT RAMP ALP GRACE Data Centers Matured Memory Models RSIM Simulator RSIM Project Publications Software Funding
		From Left to Right - Byn Choi, Siva Kumar Sastry Hari, Sarita Adve, Pradeep Ramachandran, Man-Lap (Alex) Li, Rakesh Komuravelli, Hyojin Sung Directed by: Sarita V. Adve Department of Computer Science University of Illinois at Urbana-Champaign Our group's research focus is in computer architecture. We take a full system view of the problems we solve, and so our projects are usually collaborative with faculty and students from many areas, including applications, software, and hardware. The field of computer architecture is currently undergoing several disruptive changes. Moore's law continues to bestow a wealth of transistors, but converting them into usable performance requires addressing several challenges. Industry has bet that the path to future performance benefits is through parallel (or manycore) computing. However, parallel programming remains a black art that few have been able to master. Further, it is unclear how to build manycore systems that will scale to the levels required, within the needed power budget and with the needed reliability. We are currently working on the following projects to address these challenges in a holistic fashion: DPL: Deterministic-by-default Parallel Languages (led by Vikram Adve) DeNovo: Rethinking Hardware for Disciplined Parallelism SWAT: Designing Resilient Hardware by Treating Software Anomalies Recent projects: RAMP: Reliability-Aware MicroProcessors for hard and soft errors ALP: Energy-efficient support for All Levels of Parallelism for emerging multimedia workloads GRACE: Global Resource Adaptation through CoopEration for energy in mobile multimedia systems Energy and Thermal Management in Data Centers Some of our most significant previous research contributions are in the following areas: Memory consistency models: co-developed the memory models for the C++ and Java programming languages, based on our early work on data-race-free models Hardware reliability: co-developed the concept of lifetime reliability aware architectures and dynamic reliability management Power management: co-designed GRACE, one of the first systems to implement cross-layer energy management Memory level parallelism: Some of the first papers on exploiting instruction-level parallelism (ILP) for memory system performance Evaluation techniques for shared-memory systems with ILP processors: developed the widely used RSIM architecture simulator