Sarita Adve's Research Group
University of Illinois at Urbana-Champaign


  • Our paper titled "Characterizing the Sources of Memory Stalls for Tightly Coupled GPUs" has been accepted for publication at ISPASS 2016!

  • Our Stash and Scopes papers were both awarded Honorable Mentions in IEEE Micro Top Picks 2016!

  • Sarita was elected as SIGARCH Chair!

  • Our work on Stash has been covered in the CCC blog!

  • Our paper titled "Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models" has been accepted for publication at MICRO 2015!

  • Giordano Salvador joined our research group, August 2015.

  • Matt presented Stash at ISCA 2015, June 2015.

  • Sarita was a panelist at WDDD'15, June 2015.

  • John passed the PhD qualifying exam, April 2015.

  • Sarita was elected to the Computing Research Association (CRA) board for a third term.

  • Matt presented at EPFL, April 2015.

  • Matt received the Mavis Future Faculty Fellowship Award for 2015-2016.

  • Matt received the W.J. Poppelbaum Memorial Award for 2015.

  • Rakesh presented "Eliminating On-Chip Traffic Waste: Are We There Yet?" at ISPASS 2015, March 2015.

  • Sarita gave a keynote at the 2nd Annual WACAS, March 2015.

  • Sarita presented DeNovoSync at ASPLOS 2015, March 2015.

  • Our paper titled "Stash: Have Your Scratchpad and Cache it Too" is accepted for publication at ISCA 2015.

  • Rakesh presented "Revisiting the Complexity of Hardware Cache Coherence and Some Implications" at HiPEAC 2015, January 2015.

  • Pradeep presented "Hardware Fault Recovery for I/O Intensive Applications" at HiPEAC 2015, January 2015.

  • Our paper titled "DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations" is accepted for publication at ASPLOS 2015.

  • Our paper titled "Revisiting the Complexity of Hardware Cache Coherence and Some Implications" is accepted for publication in ACM's TACO.

  • Our paper titled "Hardware Fault Recovery for I/O Intensive Applications" is accepted for publication in ACM's TACO.

     News Archive


  • Memory consistency models: Co-developed the memory models for the C++ and Java programming languages, based on our early work on data-race-free models

  • Hardware reliability: co-developed the concept of lifetime reliability aware architectures and dynamic reliability management

  • Power management: Co-designed GRACE, one of the first systems to implement cross-layer energy management

  • Memory level parallelism: Some of the first papers on exploiting instruction-level parallelism (ILP) for memory system performance

  • Evaluation techniques for shared-memory systems with ILP processors: Developed the widely used RSIM architecture simulator

Our group's research focus is in computer architecture, but we take a full system view of the problems we solve and collaborate closely with faculty and students from other areas, including applications, software, and hardware.

The field of computer architecture is currently undergoing several disruptive changes. Moore's law continues to bestow a wealth of transistors, but converting them into usable performance will require exploiting increasingly higher levels of parallelism or many-core computing. Designing parallel hardware and software that achieve power-efficient, reliable, and scalable performance, however, remains a challenge. We are currently working on the following projects to address this challenge:

    SWAT: Software Anomaly Treatment
    DeNovo: Rethinking Hardware for Disciplined Parallelism
    DPJ: Deterministic Parallel Java (led by Vikram Adve)
    Heterogeneous Computing (joint project with Vikram Adve)


Sarita Adve's Group Picture

(front) Hyojin Sung, Sarita Adve, and Matt Siclair,

(back) Siva Kumar Sastry Hari, Rakesh Komuravelli, Byn Choi, and Robert Smolinski