Sarita Adve's Group

University of Illinois at Urbana-Champaign
Sarita Adve's Research Group

NEWS

Best paper award for "DeNovo: Rethinking the Multicore Memory Hierarchy for Disciplined Parallelism" at PACT 2011!
Sarita gave a keynote speech at ICS, June 2011
Congratulations to Dr. Pradeep Ramachandran for successfully defending his Ph.D. thesis, May 2011
Sarita gave a talk at the Triangle distinguished lecture series, Duke University, April 2011
Sarita has been named ACM Fellow for the class of 2010, honored for her "impact on hardware and language memory models, and contributions to low-power and resilient systems."
"Parallel SAH k-D Tree Construction" accepted at HPG 2010
SWAT and DeNovo selected as top 10 projects to present in 2010 CS Spring Grad Expo at Illinois
An article about DeNovo appears on EETimes
"DeNovo: Rethinking Hardware for Disciplined Parallelism" accepted at HotPar'10
"A Language for Deterministic-by-Default Parallel Programming" was accepted at CPC 2010
Sarita gave a talk on DeNovo at the Illinois UPCRC Summit, Mar '10
Sarita and Hans Boehm will give a tutorial on memory models in PLDI'10

News Archive

IMPACT

Memory consistency models: Co-developed the memory models for the C++ and Java programming languages, based on our early work on data-race-free models
Hardware reliability: co-developed the concept of lifetime reliability aware architectures and dynamic reliability management
Power management: Co-designed GRACE, one of the first systems to implement cross-layer energy management
Memory level parallelism: Some of the first papers on exploiting instruction-level parallelism (ILP) for memory system performance
Evaluation techniques for shared-memory systems with ILP processors: Developed the widely used RSIM architecture simulator

Our group's research focus is in computer architecture, but we take a full system view of the problems we solve and collaborate closely with faculty and students from other areas, including applications, software, and hardware.

The field of computer architecture is currently undergoing several disruptive changes. Moore's law continues to bestow a wealth of transistors, but converting them into usable performance will require exploiting increasingly higher levels of parallelism or many-core computing. Designing parallel hardware and software that achieve power-efficient, reliable, and scalable performance, however, remains a challenge. We are currently working on the following projects to address this challenge:

    SWAT: Software Anomaly Treatment
     DeNovo: Rethinking Hardware for Disciplined Parallelism:
     DPJ: Deterministic Parallel Java (led by Vikram Adve)

(front) Hyojin Sung, Sarita Adve, and Matt Siclair,
(back) Siva Kumar Sastry Hari, Rakesh Komuravelli, Byn Choi, and Robert Smolinski