Sarita Adve's Group

University of Illinois at Urbana-Champaign
Sarita Adve's Research Group

NEWS

Our Relyzer paper is chosen for the IEEE Micro's Top Picks 2013
Our paper titled "DeNovoND: Efficient Hardware Support for Disciplined Non-Determinism" is accpeted for publication at ASPLOS 2013
Siva received the Margarida Jacome GSRC Best Poster Award, Oct 2012
Rakesh and Matt received a Qualcomm Innovation Fellowship, May 2012
Siva received the W.J. Poppelbaum Memorial Award for 2012
Byn, Hyojin, Rakesh, and Rob received the Feng Chen Memorial Award in 2012
Our paper titled "Virtual Instruction Set Computing for Heterogeneous Systems" is accepted for publication at HotPar 2012
Sarita is named Woman of Vision in innovation by the Anita Borg Institute for Women in Technology in 2012
Rob passed the PhD qualifying exam, March 2012
Rob presented CrashTest'ing SWAT at DATE 2012
Siva presented Relyzer at ASPLOS 2012
Our paper titled "Low-cost Program-level Detectors for Reducing Silent Data Corruptions" is accepted for publication at DSN 2012
Sarita has been named an IEEE Fellow for the class of 2012
Best paper award for "DeNovo: Rethinking the Multicore Memory Hierarchy for Disciplined Parallelism" at PACT 2011!

News Archive

IMPACT

Memory consistency models: Co-developed the memory models for the C++ and Java programming languages, based on our early work on data-race-free models
Hardware reliability: co-developed the concept of lifetime reliability aware architectures and dynamic reliability management
Power management: Co-designed GRACE, one of the first systems to implement cross-layer energy management
Memory level parallelism: Some of the first papers on exploiting instruction-level parallelism (ILP) for memory system performance
Evaluation techniques for shared-memory systems with ILP processors: Developed the widely used RSIM architecture simulator

Our group's research focus is in computer architecture, but we take a full system view of the problems we solve and collaborate closely with faculty and students from other areas, including applications, software, and hardware.

The field of computer architecture is currently undergoing several disruptive changes. Moore's law continues to bestow a wealth of transistors, but converting them into usable performance will require exploiting increasingly higher levels of parallelism or many-core computing. Designing parallel hardware and software that achieve power-efficient, reliable, and scalable performance, however, remains a challenge. We are currently working on the following projects to address this challenge:

    SWAT: Software Anomaly Treatment
     DeNovo: Rethinking Hardware for Disciplined Parallelism:
     DPJ: Deterministic Parallel Java (led by Vikram Adve)

(front) Hyojin Sung, Sarita Adve, and Matt Siclair,
(back) Siva Kumar Sastry Hari, Rakesh Komuravelli, Byn Choi, and Robert Smolinski