Sarita Adve's Research Group
University of Illinois at Urbana-Champaign


  • Our paper titled "DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations" is accepted for publication at ASPLOS 2015

  • Siva received the 2014 David J. Kuck Outstanding Ph.D. Thesis Award, October 2014

  • Huzaifa passed the PhD qualifying exam, October 2014

  • Our paper titled "Revisiting the Complexity of Hardware Cache Coherence and Some Implications" is accepted for publication in ACM's TACO

  • Our paper titled "Hardware Fault Recovery for I/O Intensive Applications" is accepted for publication in ACM's TACO

  • Siva presented GangES at ISCA 2014, June 2014

  • Our paper titled "GangES: Gang Error Simulation for Hardware Resiliency Evaluation" is accepted for publication at ISCA 2014

  • Hyojin received the W.J. Poppelbaum Memorial Award for 2014

  • Matt was recognized as an Outstanding Teaching Assistant for the Spring 2014 semester

  • Sarita was Program Chair for ASPLOS 2014, March 2014

  • Radha passed the PhD qualifying exam, March 2014

  • Our DeNovoND paper is chosen for the IEEE Micro's Top Picks 2014

  • John Alsop and Muhammad Huzaifa joined our research group, January 2014.

  • Rakesh and Matt present at Qualcomm Research, September 2013

  • Sarita, Hyojin, Rakesh, and Matt present talks and posters at I2PC Summit, September 2013

  • Abdulrahman Mahmoud joined our research group, August 2013

     News Archive


  • Memory consistency models: Co-developed the memory models for the C++ and Java programming languages, based on our early work on data-race-free models

  • Hardware reliability: co-developed the concept of lifetime reliability aware architectures and dynamic reliability management

  • Power management: Co-designed GRACE, one of the first systems to implement cross-layer energy management

  • Memory level parallelism: Some of the first papers on exploiting instruction-level parallelism (ILP) for memory system performance

  • Evaluation techniques for shared-memory systems with ILP processors: Developed the widely used RSIM architecture simulator

Our group's research focus is in computer architecture, but we take a full system view of the problems we solve and collaborate closely with faculty and students from other areas, including applications, software, and hardware.

The field of computer architecture is currently undergoing several disruptive changes. Moore's law continues to bestow a wealth of transistors, but converting them into usable performance will require exploiting increasingly higher levels of parallelism or many-core computing. Designing parallel hardware and software that achieve power-efficient, reliable, and scalable performance, however, remains a challenge. We are currently working on the following projects to address this challenge:

    SWAT: Software Anomaly Treatment
    DeNovo: Rethinking Hardware for Disciplined Parallelism
    DPJ: Deterministic Parallel Java (led by Vikram Adve)
    Heterogeneous Computing (joint project with Vikram Adve)


Sarita Adve's Group Picture

(front) Hyojin Sung, Sarita Adve, and Matt Siclair,

(back) Siva Kumar Sastry Hari, Rakesh Komuravelli, Byn Choi, and Robert Smolinski