Siva Kumar Sastry Hari Department of Computer Science University of Illinois at Urbana-Champaign E-mail: shari2 [at] illinois [dot] edu

I am currently a fifth year graduate student in the Computer Science Department at University of Illinois at Urbana-Champaign (UIUC). My advisor is Prof. Sarita V. Adve and I am a part of the SWAT team that focuses on developing low-cost hardware reliability solutions. I have a Master's degree from the Computer Science Department at UIUC and a Bachelor's degree from the Computer Science and Engineering Department at IIT Madras, India. I also have some industry experience through internships at Intel Labs at Intel Corporation (CA), Sun Microsystems (CA), and Design and Test Solutions group at Intel (India).

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• S. K. S. Hari, S. V. Adve, H. Naeimi, and P. Ramachandran, Relyzer: Exploiting Application-Level Fault Equivalence to Analyze Application Resiliency to Transient Faults, to appear in the Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2012.
  
  
• A. Pellegrini, R. Smolinski, X. Fu, L. Chen, S. K. S. Hari, J. Jiang, S. V. Adve, T. Austin, V. Bertacco, CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions, to appear in the Proceedings of the the Design, Automation and Test in Europe (DATE) , 2012.
  
  

2011

• S. K. S. Hari, H. Naeimi, P. Ramachandran, S. V. Adve, Relyzer: Application Resiliency Analyzer for Transient Faults, in the Proceedings of the IEEE Workshop of Silicon Errors in Logic - System Effects (SELSE), 2011.
  
  
• P. Ramachandran, S. K. S. Hari, S. V. Adve, H. Naeimi, Understanding When Symptom Detectors Work by Studying Data-Only Application Values, in the Proceedings of the IEEE Workshop of Silicon Errors in Logic - System Effects (SELSE), 2011.
  
  
• A. Pellegrini, R. Smolinski, X. Fu, L. Chen, S. K. S. Hari, J. Jiang, S. V. Adve, T. Austin, V. Bertacco, CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions, in the Proceedings of the IEEE Workshop of Silicon Errors in Logic - System Effects (SELSE), 2011.
  
  
• D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran, S. K. S. Hari, D. Sorin, A. Meixner, A. Biswas, X. Vera, Architectures for Online Error Detection and Recovery in Multicore Processors, in the Proceedings of the Design, Automation and Test in Europe (DATE), 2011
  
  

2009

• S. K. S. Hari, M. Li, P. Ramachandran, B. Choi, S. V. Adve, mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems in the Proceedings of the 42^nd International Symposium on Microarchitecture (MICRO), 2009
  
  
• M. Li, P. Ramachandran, U. Karpuzcu, S. K. S. Hari, S. V. Adve, Accurate Microarchitecture-level Fault modeling for Studing Wear-out Faults in the Proceeding of the International Conference on High-Performance Computer Architecture (HPCA) , 2009
  
  

Before 2009

• S. K. S. Hari, V. V. Konda, V. Kamakoti, V. Vedula, K. S. Maneperambil, Automatic Constraint Based Test Generation for Behavioral HDL Models in the IEEE Transactions on VLSI Systems (TVLSI) in the special section on Design Verification and Validation: Theory and Techniques, 2008
  
  
• K. Najeeb, V. V. Konda, S. K. S. Hari, V. Kamakoti, V. Vedula, Power Virus Generation Using Behavioural Models of Circuits in the Proceedings of the 25th IEEE VLSI Test Symposium (VTS), 2007
  
  
• N. Mahammad, S. K. S. Hari, S. Shroff, V. Kamakoti, Constructing Online Testable Circuits using Reversible Logic in the Proceedings of 10th IEEE VLSI Design and Test Symposium (VDAT), 2006
  
  
• S. K. S. Hari, S. Shroff, N. Mahammad, V. Kamakoti, Efficient Building Blocks for Reversible Sequential Circuit Design in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2006
  
  

• S. K. S. Hari, S. V. Adve, H. Naeimi, and P. Ramachandran, Relyzer: Application Resiliency Analyzer for Transients Faults in the Giga-Scale Research Center (GSRC) Annual Symposium, 2011
  
  
• P. Ramachandran, S. K. S. Hari, M. Li, S. K. Sahoo, R. Smolinski, X. Fu, L. Chen, S. V. Adve, SWAT: The Whole Enchilada for In-Core Fault Resiliency, at the Giga-Scale Research Center (GSRC) Annual Symposium, 2010
  
  
• S. K. S. Hari, M. Li, P. Ramachandran, B. Choi, S. V. Adve, mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicores at the Spring CS Grad Expo, UIUC, 2010. A slightly different version of this poster was presented at the Gigascale Research Center (GSRC) Annual Symposium, 2009 (pdf)
  
  
• P. Ramachandran, S. K. S. Hari, M. Li, S. V. Adve, S. Vasudevan, Application Aware SoftWare Anomaly Treatment at the Giga-Scale Research Center (GSRC) Annual Symposium , 2009
  
  
• M. Li, P. Ramachandran, S. K. Sahoo, S. K. S. Hari, S. V. Adve, V. Adve, Y. Y. Zhou, SWAT: Hardware Reliability through Software Anomaly Treatment at the Giga-Scale Research Center (GSRC) Annual Symposium, 2008
  
  
• M. Li, P. Ramachandran, U. Karpuzcu, S. K. S. Hari, S. V. Adve, SWAT-Sim: Accurate Microarchitecture-level Fault Models, at the Giga-Scale Research Center (GSRC) Annual Symposium, 2008
  
  
• S. K. S. Hari, V. V. Konda, V. Kamakoti, V. Vedula, K. S. Maneperambil, Automatic Constraint Based Test Generation for Behavioral HDL Models, University Booth at Design, Automation and Test in Europe (DATE), 2007
  
  

• Relyzer: Application Resiliency Analyzer for Transient Faults at the IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011
  
  
• Relyzer: Application Resiliency Analyzer for Transient Faults at the MDG ArchFest at Intel Corporation, Jan 2011
  
  
• mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems at the 42^nd International Symposium of Microarchitecture (MICRO), Dec 2009
  
  
• Software Managed Resiliency on behalf of Prof. Sarita Adve at the Gigascale Systems Research Center (GSRC) Kickoff meeting, Nov 2009
  
  
• MSWAT: Hardware Fault Detection and Diagnosis for Multicore Systems at the Resilient Theme Summer Workshop of Gigascale Systems Research Center (GSRC), July 2009
  
  

• M. S. Thesis: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems running Multithreaded Workloads, 2009
  
  
• B. Tech. Thesis: Automatic Constraint Based Test Generation for Behavioral HDL Models, 2007