The RAMP Lifetime Reliability Model (Version 2.0)
RAMP (short for Reliability-Aware MicroProcessors) is the first architecture-level
model that allows lifetime reliability analysis for applications and
architectures. RAMP was developed by researchers at the
After extensive discussions with device failure researchers
at IBM T.J. Watson Research Center, we incorporated five critical failure
mechanisms into RAMP 2.0 - Electromigration (EM) and Stress Migration (SM) in
the interconnects, Time-Dependent Dielectric Breakdown (TDDB or gate-oxide
breakdown) and Negative-Bias Temperature Instability (NBTI) in the
transistors, and Thermal Cycling (TC) in the package. In addition, RAMP's modular
design makes the addition of other failure mechanisms straightforward.
RAMP 2.0 models failure mechanisms with lognormal (versus the less accurate exponential) distributions, and can also model processors that are series-parallel failure systems (versus series failure). It is written in 'C++' and 'C' and can be easily interfaced with typical temperature/power/performance simulators available in the community.
Using RAMP in simulations
RAMP should be used in conjunction with a timing simulator to determine workload behavior, and a power and thermal simulator for power and temperature profiles. In addition, RAMP requires floorplan data, which is typically provided by the temperature simulator. In our files, we identify the places where data from the performance, power, and temperature simulators should be fed in. In order to obtain a proper understanding of the design and working of RAMP, the user is urged to refer to our ISCA 2004 and ISCA 2005 papers, and Jayanth Srinivasan's PhD thesis.
RAMP 2.0 was developed as part of the RAMP project consisting of:
The code in RAMP 2.0 was written by Jayanth Srinivasan and Pradeep Ramachandran.
The RAMP project is/was supported in part by an equipment donation from AMD, an IBM Faculty Award, and the National Science Foundation under Grant No.EIA-0224453, CCR-0209198, and CCR-0313286. Jayanth Srinivasan was supported by an IBM Ph.D. fellowship.
RAMP is available here under the condition that it will be used only for academic purposes. This download includes our ISCA04 and ISCA05 papers that describe the design and implementation of RAMP.
For more information, see the RAMP home page and Power and Reliability Aware Systems home page. To join the RAMP mailing list, to provide feedback on RAMP, or to contribute to future RAMP releases, please send email to ramp AT cs.uiuc.edu.