Publications
(Group publications)
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HeteroSync: A Benchmark Suite for Fine-Grained Synchronization on Tightly Coupled GPUs, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, to appear in the IEEE International Symposium on Workload Characterization (IISWC), October 2017.
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Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, in the 44th International Symposium on Computer Architecture (ISCA), June 2017.
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POSTER: hVISC: A Portable Virtual Instruction Set for Heterogeneous Parallel Systems, Prakalp Srivastava, Maria Kotsifakou, Matthew D. Sinclair, Rakesh Komuravelli, Vikram S. Adve, and Sarita V. Adve, in the 25th International Conference on Parallel Architecture and Compilation Techniques (PACT), September 2016.
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GSI: A GPU Stall Inspector to Characterize the Source of Memory Stalls for Tightly Coupled GPUs, Johnathan Alsop, Matthew D. Sinclair, Rakesh Komuravelli, and Sarita V. Adve, in the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
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Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models,
Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve,
in the 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) December 2015.
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DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism,
Hyojin Sung,
Ph.D. thesis, University of Illinois, Urbana-Champaign, 2015.
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Stash: Have Your Scratchpad and Cache it Too,
Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, and Vikram Adve,
in the 42nd International Symposium on Computer Architecture (ISCA) May 2015.
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DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations,
Hyojin Sung and and Sarita V. Adve,
in the Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015.
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Eliminating On-Chip Traffic Waste: Are We There Yet?,
Robert Smolinski, Rakesh Komuravelli, Hyojin Sung, and Sarita V. Adve,
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2015. Find an extended version of the paper
here.
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Exploiting Software Information for an Efficient Memory Hierarchy,
Rakesh Komuravelli,
Ph.D. thesis, University of Illinois, Urbana-Champaign, 2014.
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Revisiting the Complexity of Hardware Cache Coherence and Some Implications,
Rakesh Komuravelli, Sarita V. Adve, and Ching-Tsun Chou,
in ACM Transactions on Architecture and Code Optimization (TACO),
December 2014.
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DeNovoND: Efficient Hardware for Disciplined Non-Determinism ,
Hyojin Sung, Rakesh Komuravelli, and Sarita V. Adve,
IEEE Micro, special issue on the Top Picks from
the 2013 Computer Architecture Conferences, May - June 2014.
(One of twelve papers chosen.)
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DeNovoND: Efficient Hardware Support for Disciplined Non-determinism ,
Hyojin Sung, Rakesh Komuravelli, and Sarita V. Adve,
in the Proceedings of the 18th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS),
March 2013.
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Virtual Instruction Set Computing for Heterogeneous Systems,
Vikram Adve, Sarita Adve, Rakesh Komuravelli,
Matthew D. Sinclair, and Prakalp Srivastava,
4th USENIX Workshop on Hot Topics in Parallelism
(HotPar), June 2012.
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DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism,
Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, and Ching-Tsun Chou,
20th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2011, Best Paper Award.
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Safe Nondeterminism in a Deterministic-by-Default Parallel Language,
R. Bocchino, S. Heumann, N. Honarmand, S. Adve, V. Adve, A. Welc, and T. Shpeisman,
38th Symposium on Principles of Programming Languages (POPL), 2011.
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Verification and Performance of the DeNovo Cache Coherence Protocol,
Rakesh Komuravelli,
Master's thesis, University of Illinois, Urbana-Champaign, 2010.
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Parallel SAH k-D Tree Construction,
Byn Choi, Rakesh Komuravelli, Victor Lu, Hyojin Sung, Robert L. Bocchino, Sarita V. Adve, and John C. Hart,
High Performance Graphics (HPG), 2010.
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DeNovo: Rethinking Hardware for Disciplined Parallelism, Byn Choi,
Rakesh Komuravelli, Hyojin Sung, Robert Bocchino, Sarita V. Adve, and Vikram S. Adve,
Second USENIX Workshop on Hot Topics in Parallelism (HotPar), 2010.
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A Language for Deterministic-by-Default Parallel Programming,
Robert Bocchino, Vikram S. Adve, Danny Dig., Sarita V. Adve, Stephen Heumann,
Rakesh Komuravelli, Jeffery Overbey, Patrick Simmons, Hyojin Sung,
Mohsen Vakilian, and Marc Snir, 15th Workshop
on Compilers for Parallel Computing (CPC 2010).
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Memory Models: A Case for Rethinking
Parallel Languages and Hardware, Sarita V. Adve, Hans-J. Boehm,
in the Communications of the ACM (CACM).
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A Type and Effect System for Deterministic Parallel Java,
Robert Bocchino, Vikram S. Adve, Danny Dig., Sarita V. Adve, Stephen Heumann,
Rakesh Komuravelli, Jeffery Overbey, Patrick Simmons, Hyojin Sung, and
Mohsen Vakilian, in the Proceedings of the International Conference on Object-Oriented
Programming, Systems, Languages, and Applications (OOPSLA), 2009.
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Parallel Programming Must Be Deterministic By Default,
Robert Bocchino, Vikram S. Adve, Sarita V. Adve, and Marc Snir,
First USENIX Workshop on Hot Topics in Parallelism (HotPar),
2009.
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Parallel Computing Research at Illinois: The UPCRC Agenda,
Sarita V. Adve, Vikram S. Adve, Gul Agha, Matthew I. Frank,
Maria J. Garzaran, John C. Hart, Wen-mei W. Hwu, Ralph E. Johnson,
Laxmikant V. Kale, Rakesh Kumar, Darko Marinov, Klara Nahrstedt,
David Padua, Madhusudan Parthasarathy, Sanjay J. Patel, Grigore Rosu,
Dan Roth, Marc Snir, Josep Torrellas, and Craig Zilles,
Nov 2008.
Talks
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Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems, at International Symposium on Computer Architecture (ISCA), June 2017. Lightning Talk
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Coherence, Consistency, and Deja vu: Memory Hierarchies in the Era of Specialization, Keynote talk
at the High Performance and Embedded Architecture and Compilation conference (HiPEAC), January 2017. Video.
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GSI: A GPU Stall Inspector to Characterize the Source of Memory Stalls for Tightly Coupled GPUs,
at the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
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DeNovo: Energy-Efficient Memory Hierarchy for Heterogeneous Systems, at TI, January 2016.
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Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models, at 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2015. Lightning Talk
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Stash: Have Your Scratchpad and Cache it Too, at International Symposium on Computer Architecture (ISCA), June 2015.
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Stash: Have Your Scratchpad and Cache it Too, at Ecole Polytechnique Federale de Lausanne, April 2015.
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DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations, at ASPLOS 2015, March 2015.
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Eliminating On-Chip Traffic Waste: Are We There Yet?,
at IEEE International Symposium on Performance Analysis of Systems and Software, March 2015.
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Revisiting the Complexity of Hardware Cache Coherence and Some Implications, High Performance and Embedded Architecture and Compilation, January 2015.
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DeNovo: A Software-Driven Rethinking of the Memory Hierarchy,at Ecole Polytechnique Federale de Lausanne, September 2014.
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Stash: Have Your Scratchpad and Cache it Too, NVIDIA Research, July 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Cavium Networks, July 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Qualcomm Research -- San Diego, June 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Qualcomm Research -- Raleigh, June 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Oracle Labs, April 2014.
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DeNovo: A Software Driven Rethinking of the Memory Hierarchy,
University of Wisconsin-Madison, February 2014.
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Addressing the Hardware Challenges of Tightly Coupled Heterogeneous Architectures,
at Qualcomm Research, September 2013.
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Addressing the Hardware Challenges of Tightly Coupled Heterogeneous Architectures,
at Qualcomm Research, May 2013.
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DeNovoND: Efficient Hardware Support for Disciplined Non-Determinism,
in ASPLOS 2013, March 2013.
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The Imperative of Disciplined Parallelism: A Hardware Architect's Perspective.
Keynote at the 4th Workshop on Determinism and Correctness in Parallel Programming (WoDet), held with ASPLOS'13, March 2013.
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DeNovo: Rethinking the Multicore Memory Hierarchy for Disciplined Parallelism,
in the best paper session of PACT 2011, October 2011.
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DeNovo: Rethinking the Multicore Memory Hierarchy for Disciplined Parallelism,
in the "UPCRC Seminar", sponsored by Intel and Microsoft, December 2010.
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DeNovo: Rethinking Hardware for Disciplined Parallelism,
in the "UPCRC Illinois Summit", sponsored by Intel and Microsoft, March 2010.
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Rethinking Hardware and Software for Disciplined Parallelism,
in the "Advancing Computer Architecture Research" workshop sponsored by CRA/CCC, Feb 2010.
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Memory Models: A Case for Rethinking Parallel Languages and Hardware,
a distinguished lecture by Sarita Adve at University of Michigan, Feb 2010.
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Memory Models: A Case for Rethinking Parallel Languages and Hardware,
keynote talk at a plenary session of PODC and SPAA, Aug 2009.
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