Architecture Track
PhD qualifying examination
Core
1) Kenneth C. Yeager.
"The MIPS R10000 Superscalar Microprocessor," IEEE
Micro, April 1996, pp. 28-40.
2) Daniel
Lenoski, James Laudon, Kourosh Gharachorloo, Wolf-Dietrich
Weber, Anoop Gupta, John Hennessy, Mark Horowitz, and Monica
Lam. "The Stanford DASH Multiprocessor," IEEE Computer,
March 1992, pp. 63-79.
3) Dean M. Tullsen,
Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo,
and Rebecca L. Stamm. "Exploiting Choice: Instruction
Fetch and Issue on an Implementable Simultaneous Multithreading
Processor," Proceedings of the 23rd Annual International
Symposium on Computer Architecture (ISCA'96), May 1996, pp.
191-202.
4) Lionel M.
Ni and Philip McKinley. "A Survey of Wormhole Routing
Techniques in Direct Networks," IEEE Computer, February
1993, pp. 62-76.
Specialization
1) Ron Ho, Kenneth
Mai, and Mark Horowitz. "The Future of Wires," Proceedings
of the IEEE, April 2001, pp. 490-504.
2) Sarita V.
Adve and Kourosh Gharachorloo. "Shared Memory Consistency
Models: A Tutorial," IEEE Computer, December 1996, pp.
66-76.
3) Subbaroa
Palacharla and James E. Smith. "Complexity-Effective
Superscalalr Processors," Proceedings of the 24th Annual
International Symposium on Computer Architecture (ISCA'97),
1997.
4) Gurindar
S. Sohi, Scott E. Breach, and T.N. Vijaykumar. "Multiscalar
Processors," Proceedings of the 22nd Annual International
Symposium on Computer Architecture (ISCA'95), June 1995, pp.
414-425.
5) Roger Espasa,
Federico Ardanaz, Joel S. Emer, Stephen Felix, Julio Gago,
Roger Gramunt, Isaac Hernandez, Toni Juan, Geoffrey Lowney,
Matthew Mattina, Andre Seznec. "Tarantula: A Vector Extenion
to the Alpha Architecture," Proceedings of the International
Symposium on Computer Architecture (ISCA'02).
6) Trevor
Mudge. "Power: A First-Class Design Constraint,"
Computer, Vol. 34, No. 4, April 2001, pp. 52-57.
7) Brian
A Fields, Shai Rubin, and Rastislav Bodik. "Focusing
Processor Policies via Critical-Path Prediction," Proceedings
of the International Symposium on Computer Architecture (ISCA'01).
8) J.M. Tendler,
J.S. Dodson, J.S. Fields Jr., H. Le, B. Sinharoy. "POWER4
System Microarchitecture," IBM J. Res. and Dev., Vol.
46, No. 1, January 2002.
9) Jose F. Martinez
and Josep Torrellas. "Speculative Synchronization: Applying
Thread-Level Speculation to Explicitly Parallel Applications,"
Proceedings of the International Conference on Architectural
Support for Programming Languages and Operating Systems (ASPLOS'02),
October 2002.
10) Steven L. Scott.
"Synchronization and Communication in the T3E Multiprocessor,"
Proceedings of the 7th International Conference on Architectural
Support for Programming Languages and Operating Systems (ASPLOS'96),
October 1996, pp. 26-36.
11) Vinodh Cuppu,
Bruce Jacob, Brian Davis, and Trevor Mudge. "High Performance
DRAMs in Workstation Environments," IEEE Transactions
on Computers, Special Issue on High-Performance Memory Systems,
Vol. 50, No. 11, pp. 1133-1153, November 2001.
12) Marius Evers,
Sanjay J. Patel, Robert S. Chappell, Yale N. Patt. "An
Analysis of Correlation and Predictability: What Makes Two-Level
Branch Predictors Work," Proceedings of the 25th International
Symposium on Computer Architecture (ISCA'98), 1998, p. 52-61.
Compilers core and specialization
reading list
Parallel programming core and specialization
reading list
Systems core and specialization reading
list
Academic Office Qual Contact: Tony Hooker
